Accounting for Copper Surface Roughness in High Data Rate, High Frequency Designs
As noted on our website as well as various platforms across the industry, one of the biggest challenges to successfully implementing high frequency, high data rate designs is controlling loss. There are a variety of ways/areas in which loss can be manifested and accounted for during the PCB design process. One area, which relates directly to laminate material and the fabrication process, is the loss that occurs within the areas where copper comes into play. Of increasing importance is the loss associated with the roughness of copper surfaces. This blog will describe how this factor comes into play, how roughness impacts the frequency vs. loss curve, the different ways in which to control copper surface loss and the ways in which it can be accounted for within our Gauss 2D Field Solver.
But, before delving into the process of doing a sensitivity analysis at the front end of the design process, it’s important to have a clear understanding of copper and copper loss and their impact on the PCB product development process.
Overview of Copper Loss
There are three main components that can play into copper loss. They include:
- The surface area.
- The wider the trace, the more surface area there is. This contributes to reducing copper loss.
- The roughness of the copper.
- The basic conductivity of the copper (this is also affected by the metallics in the surface treatment and will be covered in a later blog post)
In contrast to dielectric loss, copper or skin-effect loss is associated with the current that flows into conductors and crowds into a thin layer near the surface at high frequencies. Similar to dielectric loss, skin-effect loss gets larger as frequencies go up. It is compensated for by increasing the width of the traces to create more surface area. A wider trace means lower skin-effect loss. In designing a PCB stackup, tradeoffs between skin-effect losses and dielectric losses are made by determining which dielectric/laminate to use and how wide the traces on the PCB will be as well as how smooth the copper surface needs to be.
The State of the State
Of the three components that contribute to loss, the ones that need to be manipulated include:
- How rough the surface is.
- How much surface (trace width) there is.
Note: Because all copper is plated, conductivity is constant across the industry and does not contribute as a variable relative to loss.
Copper Surface Roughness
The two places where the roughness can affect loss include:
- The manufacture of the foils used to create the laminate.
- During the fabrication process as the inner layers are prepared for lamination.
Copper Foils Used For Creating Laminates
One of the ways that copper foils are created is by rolling the metal through a series a of rollers that are placed ever closer together until the final thickness is achieved. The end result is a very smooth surface that does not bond well with the resins used during the PCB lamination process. This is where the need to process the foil through some kind of roughening operation to make it adhere properly during the lamination process came into play.
An alternate method for creating foil and the most common one used in the manufacturing of the foils that are used in multilayer PCBs is to electroplate copper onto the surface of a drum that is partly submerged in a plating solution. As the drum turns, the copper is plated onto the surface of it. When this plated copper emergences from the plating bath it is peeled off the drum as continuous sheets of copper.
The advantages of this process is that the foil can be any length; it can be plated to any thickness with a great deal of uniformity and the surface of the foil that faces the drum can be made to any roughness by etching the surface of the drum.
However, when the surface of the drum has been roughened enough to provide proper adhesion between the side of the foil and the laminate, the non-drum side of the foil will still be too smooth for proper adhesion.
Initially, the methods for roughening included:
- Using a pumice scrubbing machine.
- This left scratches in the copper surface that often resulted in open circuits with thin copper foils.
Pumice scrub was replaced by black oxide which is a process that chemically etches the copper surface to promote adhesion.
- When the foil created by this process is examined under a microscope, it looks like there are sharp peaks and valleys that have been etched into the copper. It works well for adhesion but when two pieces of copper are laminated back-to-back across a thin piece of laminate, the height of the peaks are such that plane-to-plane shorts can occur.
To counteract this problem, a bond film of some kind is used to promote adhesion during processing.
Processing Inner Layers For PCB Manufacturing
The signal and power layers of a PCB start out as solid sheets of copper foil. These copper sheets are bonded to sheets of glass cloth that have been saturated with resin. The combination of the two sheets of copper foil, one on each side of the glass/resin is placed in a press and then the temperature is elevated so that the resin sets. The significant problem has been finding a way to ensure the resin bonds to the copper foil with enough strength that the layers won’t delaminate during use and pads won’t lift away during the rework process.
Historically, copper was made rough so that it would bond to the laminate. The problem was that this rough copper produced quite a bit of loss. But, because loss was not an initial area of concern, the roughness of the copper was often ignored. Figures 1 and 2 shows the difference between smooth and rough copper. Figure 1 is the smooth copper and Figure 2 is the rough copper.
Figure 1. Very Low Profile Copper Foil (VLP)
Figure 2. Reverse Treat Copper Foil (RTF)
When copper surface roughness became increasingly important, the industry pushed for the very smooth or very low profile (VLP) copper. Despite the innovation of VLP copper, the copper surface in use today still has irregularities in the forms of peaks and valleys which continue to contribute to loss. Back in the day when copper was made rough to ensure that it would bond to the resin, the height of the roughness was 8 or 10 microns. Smooth copper has a roughness of 2 microns but it still contributes to loss. And, there has to be some way to model these contributors (more about this later).
Eventually, a whole new set of chemistry was developed to make the smooth copper bond to the resins during lamination.
How Rough Is Too Rough?
Before delving into the specifics about performing a sensitivity analysis, it’s worthwhile to examine just how copper surface roughness can impact a PCB.
Two boards can be essentially the same and have very different loss vs. frequency curves. For example, Figures 3 and 4 show shows the loss versus frequency curves for two PCBs made from the same material and the same artwork but was manufactured at two different fabricators. At 8 GHz the loss for the board on the left is 35 db and the loss for the board on the right is 40 db. This is a substantial difference, even though both boards were made using the same laminate and the same artwork.
Figure 3. Loss vs. Frequency (Smooth Finish)
Figure 4. Loss vs. Frequency (Rough Finish)
Figure 5. PCB Finish for Figure 3.
Figure 6. PCB Finish for Figure 4.
Figures 5 and 6 show the difference in copper surface roughness of the two PCBs shown in Figures 3 and 4. As can be seen, the copper roughness of the PCB shown in Figure 4 is much greater than that shown on the PCB in Figure 3. The difference is due to the ways that the fabricators treated the surfaces of the traces and planes prior to lamination. Prior to now, the primary driving force for the fabricator in copper roughness was to ensure that delamination did not occur until assembly. To prevent it from happening, the surface was roughened to the point that it ensured that there would be good adhesion between the resin in the prepreg and the copper of the planes and traces. The differences between the PCBs was the amount of surface roughening that was done at the fabricators.
What About Today’s High Frequency, High Data Rate PCBs?
In today’s high-speed designs such as those characterized by 112 Gbps/channel and 5G/mmWave applications, there is very little “wriggle room” for error and the design parameters are extremely rigid. One of the challenges in today’s design environment is that a lot of the commercially-available simulation tools understate copper loss. This leads product developers to assume that the dielectric losses in their PCBs are higher than they really are. The reality is that the emphasis for today’s products is on lower and lower loss. This means that being able to squeeze even five or ten percent out of loss becomes a predominant design factor.
However, the reality is we have pretty much hit the end of the road in terms of how much lower the copper roughness or oxide roughness can be. The challenge is that the solution to this problem lies with the oxide and copper suppliers.
What all the foregoing means is that accounting for copper surface roughness becomes a prominent design criterion. The best way to address this issue in today’s “unforgiving” environment, is to perform a sensitivity analysis during the early stages of the design process.
Lee Ritchey, the Founder and President of Speeding Edge and one of the industry’s predominant high-speed design experts provides the following recommendations. “I take the longest path in my design and then model the loss as a function of two different variables—the loss of the dielectric and the loss in the copper with the goal being to not over or under specify materials. If you under specify you have to throw the whole board away. If you over specify, the board becomes more expensive and the choice of available materials becomes very limited. This can lead to a sole-source situation which I always try to avoid.”
Gauss 2D Field Solver Advantages
With today’s high frequency, high data-rate designs, because of skin effect, the current in the plane occupies about the same amount of copper width of the trace or a little bit more. This means that a product developer can expect to see a similar loss in the plane as there is in the trace.
Until now, it’s not been possible to get a loss curve correlation between the measured loss and the loss information obtained from the simulator. No tools were able to account for loss in the plane. Over the past few years at DesignCon, a number of EDA vendors have tried to model loss. However, they were just modeling the loss in the trace and not including the loss in the plane. With today’s high frequency designs, the current gets increasingly crowded under the trace and, previously, no toolset has done a good job of predicting how much the current is spread throughout the plane. The higher the frequency, the more important it becomes to account for this factor. Until now, the only approach to the solution was for product developers to build a test board and, then if the PCB performance capabilities did not meet the design requirements, go back to square one and start all over again. This would lead to high NRE costs, extended product development time, missed market opportunities and overall reduced product profitability.
Gauss 2D Field Solver
The Gauss 2D Field Solver offers all of the capabilities and functionality of traditional 2D field solvers but goes one step further by offering a greater level of granularity and accuracy not found in traditional 2D field solver toolsets. In addition to being a field solver Gauss 2D is also a fully frequency-dependent tool that allows the SI engineer to look at all of the properties of interest including impedance, loss, propagation delay, effective dielectric properties that include the effect of the roughness, and full RLGC. Gauss 2D also includes a causal roughness model that takes the roughness effect on the imaginary inductance of the component into account. With Gauss 2D, the PCB product developer can set up their design to allow one variable to move through a range of a particular factor such as loss and see what the effect of that variable is on loss. Copper finish and dielectric loss are the two variables that are analyzed in Gauss and then based on the information provided by the toolset, the designer can determine how rigid their PCB design will need to be to control these factors.
The analysis undertaken in Gauss 2D is done post stack-up so that the information obtained more closely aligns with the final, as-built PCB. When a need for change is found in Gauss 2D, that information is iterated back to Gauss Stack so that the appropriate changes can made to the design configuration. This is done as a “what if” process where design changes are made in Gauss Stack and then those are forwarded to Gauss 2D so that the changes can be fine-tuned to reach the final, ideal configuration of the PCB. The goal of this process is to optimize the design process and reduce the number of design iterations, respins and delays in product manufacturing which, in turn, can affect the overall viability and profitability of the end product.
Kella Knack currently serves as Director of Strategic Marketing for Avishtech, a leading provider of EDA software design tools–Gauss Stack and Gauss 2D. She assists in the company’s marketing communications, positioning, tradeshow, PR and outbound messaging efforts.
Prior to this, she served as Vice President of Marketing for Speeding Edge, an engineering consulting and training company focusing on the design of high speed PCB and system design. She oversaw the redesign of the company’s website; implemented the establishment of Speeding Edge as a publishing company; developed all of the company’s marketing materials and managed tradeshow activities. She also established key strategic relationships in Germany and Denmark and oversaw the expansion of the company’s presence in Europe, Canada and Asia. In addition, she served as editor and coordinated all layout and printing efforts for the publication of the company’s two technical books, “Right the First Time,” Volumes 1 and 2.
Before this, she was the Founder and President of KJ Communications, Inc., a marketing consulting and public relations company based in Silicon Valley. She served as a strategic adviser for a number of highly successful marketing campaigns for clients that ranged from start-ups to multimillion dollar companies in the EDA, networking, SOC IP, semiconductor, embedded system design and database management market sectors. Once the programs were defined, she assisted these clients by coordinating their press activities; preparing press releases and assisting with the development of other marketing materials. Before this, she was an editor of various industry technology publications including PCB Design, LAN Computing and ASIC and EDA Magazine.