Avishtech Thought Leaders: Heidi Barnes, Keysight Technologies
Heidi is presently Senior Applications Engineer and Power Integrity Product Owner for Keysight’s Design Engineering Software Group. Her vast experience and knowledge base and her commitment to sharing both with young engineers at industry conferences makes her one of the undisputed thought leaders when it comes to identifying and solving power integrity issues.
Keysight is legendary in the world of electronics, with roots in test and measurement. The original company was founded by Bill Hewlett and Dave Packard. Over the years, the company’s name has changed from HP to Agilent, and now to Keysight, but the leadership in electronic measurements and simulations remains the same. Keysight is bringing new focus to the company with integrated solutions for industry applications. Integration of simulation and measurement data, as seen in Keysight’s PathWave technology, provides valuable management of a product’s full life cycle from design, through hardware test, and production.
The company is based in Santa Rosa, California; has 20 R&D sites worldwide; 32,000 customers in more than 100 countries; and a global total of approximately 14,300 diverse employees. Keysight delivers advanced design and validation solutions that help accelerate innovation to connect and secure the world. Keysight’s dedication to speed and precision extends to software-driven insights and analytics that bring tomorrow’s technology products to market faster across the development lifecycle, in design simulation, prototype validation, automated software testing, manufacturing analysis, and network performance optimization and visibility in enterprise, service provider, and cloud environments. Its customers span the worldwide communications and industrial ecosystems, aerospace and defense, automotive, energy, semiconductor and general electronics markets. Keysight generated revenues of $4.9B in fiscal year 2021. Additional information about Keysight Technologies (NYSE: KEYS), can be found at the company’s website: https://www.keysight.com/us/en/about.html.
About Heidi Barnes
As noted above, Heidi is a Senior Application Engineer and Power Integrity Product Owner for High-Speed Digital applications in the Design Engineering Software Group of Keysight. Her recent activities include the application of electromagnetic, transient, and channel simulators to solve signal and power integrity challenges. She is the author of over 20 papers on SI and PI; is an active member in developing the new IEEE P370 Standard involving interconnect S-parameter quality after fixture removal and was the recipient of the DesignCon 2017 Engineer of the Year.
Her prior experience includes seven years in signal integrity for ATE test fixtures for Verigy, an Advantest Group; eight years in RF/Microwave microcircuit packaging for Agilent Technologies, ten years with NASA in the aerospace industry, and one year with Arco Solar in the solar cell industry. She has been with Keysight EDA software since 2012. She holds five patents and was awarded the NASA Silver Snoopy for her work on hydrogen fire and gas detection.
The Specific Focus
In working with Keysight’s PathWave ADS with PIPro for Power Integrity Applications Heidi notes, “This is an EM tool that leverages net and component information in an imported PCB layout to automate the EM setup of simulating a power delivery network. The tool encourages good engineering workflow by starting with DC IR drop tools to ensure basic voltage level margins are met and investigate current densities and electro-thermal issues. Part of the automation is that the DC IR drop setup can then be copied to an AC analysis and capacitors identified for completing the setup and simulation for a full AC S-parameter model of the PCB PDN. The AC model can then be used with the Decap optimizer to minimize the quantity of capacitors to reach a desire target impedance. Recently, for the ADS 2022 Update 2.0, we added the capability to do Conducted EMI. This new feature automates the generation of a digital twin EMI test bench complete with a large signal dc/dc converter switch model, differential excitation of the PCB EM model, and fast steady-state solutions with harmonic balance. This new EMI capability is initially targeted at the automotive industry which has some of the toughest requirements for EMI with the CISPR 25 standard in the US, and EN55025 in Europe. For the FM band in the CISPR 25 test, there’s only 8mV of allowed noise on the power cables.”
What’s Driving The Need for PI Simulation?
Heidi explains, “There are two specific industries that are driving the need for PI simulations:
- Automotive with the density of electronics and massive amount of data processing required.
- Internet Infrastructure with server farm CPU’s pulling hundreds of amps with high-speed data links that use multi-level signaling with power rail voltages that keep dropping. “
“Both of these applications continue to drive electronics to lower operating voltages and higher currents that decrease the available design margins for power delivery. “Obviously, these applications show up in US, Asia, Europe etc., so I see more of a general growing interest worldwide in simulation for power integrity. It is also exciting to see the expansion of chip manufacturers to multiple sites around the world. This will only increase the creativity of electronics and fuel the exciting growth in consumer and industrial applications.”
Heidi continues, “The market segments utilizing PI tools always surprise me. Everyone needs power, and most applications have some digital circuitry, so this means there is not just one market sector driving the sales. The biggest challenge for Power Integrity is getting people to use simulation to engineer the power delivery, rather than just leveraging a design and hoping it works. Typically, it is the larger companies or ones with the most risk that are the first to invest in the emerging simulation technologies for Power Integrity.”
“Our Power Integrity focused EM simulator, PIPro, has opened the door to the average SI and PI engineer who doesn’t have time to be an EM guru, but is feeling the pain of PCB parasitics impacting their power delivery design margins. Failing to check the impact of the PCB layout on the power delivery network can often result in hardware failures from PDN resonances. It’s better to simulate early in the design phase and include post layout EM models before going to manufacturing.”
Common Mistakes and Single Points of Failure
“The biggest mistake engineers make is not simulating their design and just leveraging it without any engineering analysis to verify it works for their application,” Heidi explains. The second biggest mistake is not verifying the vendor model with measurement. Capacitor models are very challenging since they often include that PCB mounting inductance that the EM simulator of the PCB is also calculating for the PCB footprint. If the capacitor vendor model is used with the EM model, then the mounting inductance is counted twice and this can result in overdesigning with too many capacitors.”
In terms of single points of failure, Heidi notes that the idea of “’Knowing what you are buying’ is key. For instance, there is this idea that a ferrite bead is going to help reduce noise. They have their use, but so many PI engineers fail to verify that these very high Q devices are not resulting in potential resonances on the PDN they are trying to isolate. Just think about it, the PI engineer needs high frequency power delivery and is fighting the inductance in the path that will result in voltage ripple from the simple equation that L times di/dt is voltage. Adding a ferrite bead adds inductance that then requires more capacitors to be added to provide the higher frequency charge storage for the load. Further, selecting the wrong capacitors can create resonances with the ferrite.”
When initiating the PDS design process, Heidi explains, “How to find the Target Z is typically the first question. It’s very rare to find this information on a vendor datasheet. Datasheets prefer to state allowed p-p voltage ripple, not the actual target impedance that is required for the dynamic load. I am teaming up with Steve and Jack again this year at DesignCon to address this specific topic with our paper ‘Practical Methods of Estimating Dynamic Current for Calculating PDN Target Z.’
Author’s Note: On virtually all current designs, half of the logic signals have to be routed over the Vdd planes. Whatever ripple is on the Vdd plane will also be on the logic signals. How much noise the logic signal can tolerate will determine the ripple target for the PDN design. Until the advent of super low Vdds, it has always been the logic signals that set this PDN ripple target. At .9 volts, the allowable ripple on the core is around the same number as the one noted above. When data sheets state p-p voltage ripple, it ignores these other factors such as ripple on the signal lines.
What About The PDN Design-To-Test Process?
Within the industry, there is increased emphasis on the design-to-manufacturing processes and the factors that influence them. The PDN design-to-test process is even more convoluted as identifying what is important to the test process during the design phase requires an even broader overall product vision.
Heidi notes, “Design to test for Power Integrity is an interesting story, when I first started focusing on PI applications in ADS about six years ago my favorite question for a PI engineer was: ‘If you design for Target Z, do you also measure the PDN Z of the finished product?’ Surprisingly, the answer was usually no. That does not help the design-to-test link concept. More recently, I have demonstrated that with a digital twin type test bench using an EM model of the PCB and measured models of the components, one can get good correlation with power rail ripple between simulation and measurement. This was also a focus of the DesignCon 2020 paper ‘A Method for Dynamic Load Current Testing with a Benchtop Power Supply’ that I co-authored with Steve Sandler of Picotest, and Jack Carrel of Xilinx.”
“When it comes to quality issues, I would have to harp on Steve Sandler’s biggest advice for power delivery design,” she declares. “It is not just about staying below a target impedance. PI should also be about designing for flat impedance vs. frequency. Flat impedance is far more tolerant of component variations and provides for repeatable product performance, which is the definition of better quality. A Power delivery network with resonances, even if small, can still be very sensitive to component tolerances leading to performance variation. In the RF/uW world of Faraday’s telegrapher equations it is the idea that matched impedance will reduce reflections and maximize power delivery efficiency.”
“To counter this, simulation tools make it easy to do Monte Carlo simulations to look at the impact of component tolerances. This helps to also identify which components are the critical ones and may require tighter tolerances or design changes that can reduce the sensitivity.”
Current Trends That Impact Manufacturing Test Operations?
Similar to the gap between the design and manufacturing processes there are also significant gaps between the PCB manufacturing and downstream test operations process. Heidi states, “The biggest problem for the Power Integrity engineer are the old-fashioned Power Electronics methods of measuring power supply stability that require breaking the feedback loop to look at the open and closed loop behavior. This is impossible on power ICs or modules with no access to the control loop and the internal workings of the dc/dc converter, and yet gain and phase margin requirements are often a pass/fail requirement for a design. This is one of the reasons for pushing for measuring PDN impedance. The output impedance of the regulator measured at or near the first bulk capacitors in the on and off state can provide a lot of information on the stability of the power supply. Steve Sandler has a Non-Invasive Stability Margin algorithm that is available on the Keysight E5061 network analyzer that uses the impedance measurements to calculate the gain and phase margins in applications where it is not practical to access the feedback loop.”
As is being readily acknowledged across the industry, the increasing complexity of high frequency, high data rate designs are impacting current test processes. With this in mind, the question arises as to if there will be a point in time when conventional testing products and practices will no longer be effective.
Heidi explains, “I think the biggest change we see going forward is the need for simulation and measurement to work closely together. Measurement is often limited in access to what can be measured without disturbing the operation of the product. Simulation is often challenged with what level of fidelity is needed for the models to correlate with measurement. Bringing the two together can overcome these individual challenges. Measurement at one location can verify the simulation model and then the simulation model can predict performance at a location or under a condition that measurement cannot access. This was the focus of the paper I mentioned earlier on measuring dynamic current at the FPGA. Without a good EM simulation model of the PCB, the synthesized dynamic current from dynamic voltage measurements would not have been possible.”
“We are continuing our efforts to automate the Power Integrity engineer’s workflow to make it more accessible and easier to use – not just for the experts – but also for the general-purpose hardware engineer. This includes the requirement to get out there and complete webcasts and conference presentations to educate the industry on the benefits of end-to-end power integrity.”
As with other elements within current and future products, the combination of lower voltages and higher currents significantly decrease the available design margins for power delivery. When these factors are combined with current production challenges and component availability, the need to get power integrity right the first time, becomes an ever-greater imperative. This can be accomplished through the use of leading-edge technology that helps product development engineers address these factors early on during the design process. Continuing education as to the types of PI problems being encountered and how to address them also factors into the equation.
For all of the reasons noted above as well as several others that Avishtech addresses in its Gauss toolsets, today’s high frequency, high data rate designs are more completely and successfully realized when a comprehensive, thorough simulation effort is established at the onset of the product design process. Presently, these designs leave very little “wiggle room” or latitude for design missteps however minor they may seem. This mandates the ongoing optimization of today’s toolsets and continuing efforts to enhance their capabilities.
Kella Knack currently serves as Director of Strategic Marketing for Avishtech, a leading provider of EDA software design tools–Gauss Stack and Gauss 2D. She assists in the company’s marketing communications, positioning, tradeshow, PR and outbound messaging efforts.
Prior to this, she served as Vice President of Marketing for Speeding Edge, an engineering consulting and training company focusing on the design of high speed PCB and system design. She oversaw the redesign of the company’s website; implemented the establishment of Speeding Edge as a publishing company; developed all of the company’s marketing materials and managed tradeshow activities. She also established key strategic relationships in Germany and Denmark and oversaw the expansion of the company’s presence in Europe, Canada and Asia. In addition, she served as editor and coordinated all layout and printing efforts for the publication of the company’s two technical books, “Right the First Time,” Volumes 1 and 2.
Before this, she was the Founder and President of KJ Communications, Inc., a marketing consulting and public relations company based in Silicon Valley. She served as a strategic adviser for a number of highly successful marketing campaigns for clients that ranged from start-ups to multimillion dollar companies in the EDA, networking, SOC IP, semiconductor, embedded system design and database management market sectors. Once the programs were defined, she assisted these clients by coordinating their press activities; preparing press releases and assisting with the development of other marketing materials. Before this, she was an editor of various industry technology publications including PCB Design, LAN Computing and ASIC and EDA Magazine.