New to our series of blogs are those that we are identifying as Thought Leader Articles. Here, we work with several well-known individuals who are highly esteemed for their particular expertise as it applies to the PCB product development process. With the increasing need to have more visibility and control into the downstream processes post design, we believe that they provide information that can be useful for current and next-generation designs be they defined as leading edge, high speed, or high data rate, high frequency designs.

When it comes to naming those individuals who are perennially identified as the war horses of the PCB industry, one name that is always at the top of the list is Lee Ritchey. And, he has the battle scars to prove it. Lee is the Founder and President of Speeding Edge where he specializes in consulting and training for the design of high-speed PCB systems. Lee’s longevity in the industry as well as his continuing involvement in “leading edge” products, enables him to provide a wide range of perspectives especially when it comes to successfully spanning design-to-manufacturing-to-assembly operations.

About Speeding Edge

Founded in 1994, Speeding Edge provides training and consulting for the high-speed PCB and system design industries. The company’s training courses focus on “real-world” engineering challenges with data derived from a combination of computer simulations and laboratory testing. The goal of this training is to provide engineers with information they can immediately apply to their current or next-generation design projects. In addition to its training courses, the company offers engineering consulting services with expertise ranging from very high-speed differential signaling to electromagnetic interference (EMI) and signal integrity issues including power distribution system design. Current project consulting efforts focus on getting to 28 GB/S and beyond for high bandwidth networking products. Speeding Edge’s consulting services have covered a broad spectrum of technology areas including next-generation satellite processor cores; camera subsystems; next-generation telecommunication access products, medical products and hand-held data capturing devices. The company is based in Bodega Bay, California.

About Lee Ritchey

Lee’s venture within the electronics industry started in 1960 when he was hired as a technician. His first job as an engineer was for the Apollo space program in 1967. From there, he went into Silicon Valley just as it started to become Silicon Valley.

He declares, “I have been witness to all of the product development from year one of Silicon Valley. The first time I designed a product that was called high speed, the clock was 33MHz. We weren’t sure that we could make it work at that speed. The technology was ECL and it was used for building a computer at Amdahl.”

Following that project, Lee served in a variety of positions, including being in charge of manufacturing engineering for Finnegan in building mass spectrometers and Comprint that was manufacturing printers. He also oversaw the design of numerous of commercial and aerospace products that could be readily classified as “pushing the envelope” during the day.

During the 1980s, Lee’s time was spent with a design-services company, Shared Resources, that he cofounded and managed for more than 12 years. During that time frame, Shared was involved in a number of very challenging engineering design projects, including all of the PCBs for the first five years of SUN Microsystems products.

Following his tenure at Shared, Lee went to Maxtor, a disc drive company, which he defines as “my experience in high volume manufacturing.” Next, he went to work at 3Com where he was the company’s roving, world-wide technical expert for all the high-speed PCBs being developed for a broad spectrum of network management products.

Following 3Com, Lee founded Speeding Edge. Once again, as an engineering consultant Lee was at the forefront of next generation technology. Procket was his first big client and it was making the first terabit router with shippable product initially delivered in 2001. After Procket, he consulted for Mahi Networks. He explains, “Mahi’s product was more or less the same kind of router but it’s customer focus was Telcos. These two efforts represented the evolution that was happening within the industry. The Procket machine had thousands of 3.125 GB/S links on the PCBs and 50 10 GB/S outputs. Mahi’s machine was double that.

In addition to engineering consulting, a lot of Lee’s time throughout his career has been devoted to training. He has taught classes to more than 11,000 engineering students through industry conference events, sponsored seminars and classes directly hosted by Speeding Edge. In addition, Speeding Edge expanded his efforts outside the U.S. through strategic partnerships in Europe, Asia, Australia and Africa.

He has also been active in a number of standards bodies. He notes, “For years, I was on the IPC committee that maintained the high-speed design handbook. In the late 90s, I wound up as a reviewer for DesignCon which I have continued to this day.”

A Brief History of Component Technology

In terms of his experience with various component technology, Lee explains, “ECL marked the first transition to ‘high-speed’ systems. For a time, the industry relied on both ECL and, to a lesser extent, GaAs. But, both of these classes of devices consumed so much power that there was a limit to how big you could really make something because of the amount of heat that was generated. This led to the development of CMOS. Early CMOS was really slow so it wasn’t much of a player until the late 1980s when we hit the limit on how big we could build something with ECL. At the same time, we were learning how to build fast CMOS.”

Today’s Design Challenges

With today’s designs, regardless of the product being designed and the market sector(s) for which they are being developed, the goal is always the same: having a better understanding of all of the downstream processes and addressing them early on in the design phase optimizes product manufacturing, operation, reliability and profitability.

Lee explains, “Right now, I am working with a long-term client that is just starting up the speed curve and they don’t understand how the various material characteristics will impact their product. They’re getting ready to build boards with 3 GB/S links and this is right on the boundary where you have to worry about skew, vias and loss. Skew and loss are directly related to laminate properties. This is an instance where Avishtech’s toolsets could be beneficial because they will let engineers accurately model the physical and performance characteristics of the product.”

(Note: Among their functionalities, Avishtech’s tools enable “what if” simulations and predictions based on the various laminates being considered.)

Lee continues, “What we say is we have to make paths X inches long at a given frequency, and we are allowed so much loss. With a tool like Avishtech’s Gauss Stack, it is possible to model the path to see if we can achieve that loss number.”

As Lee notes, when companies are starting up the speed curve, there are a number of challenges that come into play from both a technical and a business aspect. He explains: “These companies are ignorant of the things they have to start worrying about. For example, a company can spend hours agonizing over what Tg they should have. I think they are under the impression that Tg matters at normal operating temperatures. It doesn’t. It matters when you are soldering. If the laminate expands too much, you end up fracturing the copper in the PTHs. Or, if you have a design with stacked vias, the laminate expansion can cause the stacked vias to break open.” (More about stacked vias below).

Note: Tg is a property of most resin systems that are used to fabricate PCBs. It’s the temperature at which the temperature coefficient expansion of the resin changes from a modest rate to a very high rate of expansion. PCBs heated to temperatures above the Tg of the resin system are subject to via failures due to excessive stress in the “Z” axis.

If a company has been designing lower performance products for a long time and then starts designing high-speed products it can run into significant business challenges. Lee explains, “When a company has one or more divergent product lines, there can be a disconnect between the protocols used for those products I would identify as lower performance and those that are high speed. In terms of the lower performance products, the focus is on using the cheapest materials possible. And that is the route the purchasing department is told to follow.”

He continues, “But, when you are designing a high-speed product, you need to worry about controlling skew and loss so the product development engineers end up having to fight with their own purchasing department to buy a laminate that is going to meet their criteria. I have done training sessions in companies with the manufacturing engineers and the materials purchasing people getting together so they could understand why certain requirements were being added. I keep telling my students that they have to train the purchasing people.  That has to be part of their job. When they complain that the purchasing people aren’t getting it right, it’s not fair. They [purchasing people] can’t be criticized for something they don’t understand.”

With an Eye to The Future

Describing the types of challenges that the industry will be facing between now and five years out, Lee cites a couple different factors.

“The topic of stacked vias will grow in importance. Vias in cellphones aren’t a problem because, although they are stacked, the dielectric thickness is one or two mils. It’s the market where multiple boards with stacked vias are being used such as those found in numerous aerospace products that is challenging. In these product implementations, there can be two 16-layer boards and they will be laminated together to create a 32-layer board. Every one of the vias are stacked vias and they are failing. This is where Avishtech’s Gauss Stack tool could be very beneficial because of the ability to simulate and predict whether vias should be stacked or staggered and what the single points of failure can be. Having that information available during the design phase can make all the difference between a board that is buildable and reliable and one that is not.”

When it comes to component technology and the ability to maximize its performance, Lee explains, “On the speed front, for a while, we have been hitting the limit on what we can get the silicon to do. As has always happened, what we are going to have to do to get more performance is to start making things parallel. That’s what 400 GB/S links are. They are eight 56 Gb/S links that get combined onto one fiber. The industry is trying to take that 50 GB/S clock and then utilize PAM4 to double it to achieve 112 GB/S. But, there’s a noise margin problem with PAM4. So, the question is how do you make it robust enough to be used?”

“And, as far as the Internet is concerned, I don’t know how we double the speed of silicon one more time. With 56 GB/S, you have to go up and come back down in less than 20 picoseconds. Getting I/O that is faster than that would seem impossible. But, every time I have said, ‘you can’t do that,’ somebody’s figured it out. However, it’s important to remember it’s not just about designing it, you have to be able to build it.”

He adds, “Inside the parts, there are rise times that are under 10 picoseconds but they are driving lines that are a millimeter long. That’s not the same thing as driving a 50-Ohm line that is ‘X’ centimeters long.”

From a product implementation standpoint, Lee sees some changes starting to happen. “I kind of think the real big demand on the Internet, which was to build out the bandwidth so it could do all these remote meetings, is close to being done. So, I expect that part of the industry will slow down somewhat. Of course, 5G is driving all that but it’s not available everywhere. Certainly, for high resolution video you need all that bandwidth.”

He adds, “Five years from now we will be dealing with those products that we didn’t use to think of being high performance. Those are all coming up the curve and product developers are going to need the training so they can understand how to make manufacturable products. What no one predicted was PCI Express being used in just about every product except PCs. For example, in one project, which is used in the optical inspection of wafers, the complexity is so high that the data coming out of imaging is all on 16 GB/S PCI Express that is thirty channels wide.”

Summary

With the complexity of today’s high data rate, high frequency designs, there is an ever increasing imperative to look at the downstream processes—manufacturing, assembly and test during the design cycle and the earlier, the better. There are a number of factors and skillsets that come into play to make all this happen. Designs have to be thoroughly simulated and predicted to determine what is “doable” and “buildable”; toolsets have to address these issues with more granularity and accuracy and communication across all sectors of the product development process needs to be optimized.