Plated Through Hole Reliability Simulation

Perhaps one of the most critical failure modes in PCB design and development is that of failure of Plated Through Holes, so much so that one of the central testing batteries to the test vehicle landscape is that of observing whether or not the Plated Through Holes on a PCB failed at the end of a test consisting of several reflow cycles, followed by a set number of thermal cycles between two predetermined temperatures – the most common spec (as laid out in IPC TM-650) for this is to put the boards through 6 reflow cycles at 260 °C, followed by 1000 thermal cycles between 25 °C and 150 °C. With Gauss Stack, you can simulate the survival of your board’s PTHs and determine the median life to failure.

Reflow, Thermal Cycling, & Service Conditions

To this end, Gauss Stack allows you to simulate these key failure modes by looking at either Reflow survivability, Thermal Cycling reliability, Accelerated Testing Conditions (Reflow + Thermal Cycling) or, especially relevant in certain Military and Aerospace applications, Service Life after Accelerated Testing Conditions (Reflow + Thermal Cycling + Service), catching overstress conditions for Reflow survival and determining fatigue failure points for Thermal Cycling and Service Conditions and providing you with Stress and Strain curves. Additionally, Gauss Stack has several predefined Service Conditions and can take the median life to failure estimates one step further to provide you with median life to failure in terms of years of expected operating life. Gauss Stack will provide you with a clear picture in seconds, so you can Computationally Prototype your boards for Plated Through Hole Reliability without ever having to build a test vehicle board!