Welcome to the Avishtech Blog!

Welcome to our blog site. Our goal with this first series of blog posts is to provide real-world information regarding the challenges associated with designing high frequency, high data rate designs and to cover topics from a variety of perspectives with a focus on the properties and characteristics of dielectric materials as relate to executing them. We will address the technical issues associated with creating these designs with respect to material choices; the different design criteria that are crucial to successful design execution; and the evolution of these designs going forward. Our blogs are meant to be informative, educational, and, above all, take the “technology high road” to provide real insights that will help you successfully execute your designs. Through this series, in addition to providing information on our toolsets and the various capabilities found within them, we will turn to various industry experts who have a broad base of experience in executing these designs and can speak to the “real world” challenges, especially from the dielectric materials aspects, as they relate to the design process. To that end, our first blog post is from Lee Ritchey, Founder and President of Speeding Edge.

Lee is considered to be one of the industry´s premier authorities on high-speed PCB and system design. He conducts on-site private training courses for high technology companies and is a valued and esteemed presenter and educator at industry trade shows and technical conferences. In addition, he provides consulting services to top manufacturers of Internet and server products. As a lecturer and instructor, Lee’s experience within the industry is unique. He has held several consulting as well as corporate positions where he was responsible for overseeing the successful design and then fabrication of a variety of PCBs including those initial boards that were designated as high speed because they had to operate at the then very high speeds of 2.5 Gbps. When presented with design guidelines or “rules-of-thumb” relative to high-speed design, Lee’s response always is, “show me the hardware that backs up your claims.”

 In 1998, he was profiled by EE Times as “the high-speed design ratchet man.” We are grateful to have Lee’s comments and perspective on the history of PCB laminates and the challenges associated with them as they relate to the direction of high frequency, high data rate designs not only now but going forward.

We welcome any questions, input or comments you may have regarding our blogs. You may also suggest blog topics to us at info@avishtech.com. Thanks in advance for your time and consideration and we hope you enjoy these posts!

—Keshav Amla, Founder and CEO, Avishtech

When it comes to designing high frequency, high data rate products, there are a number of ways in which the laminate you choose for your product can affect its performance. As we continue to go up the speed curve, these parameters become more important. The following is an overview of those laminate characteristics; when they started to become a factor and the role they play in today’s designs and beyond.

For PCB designs, there are about 10 different dimensions that have to be taken into account when you are selecting a particular laminate. Among them are how long the trace is, what the data rate is and how much noise margin the logic family has. The only way to determine these impacts is to compare the choices of laminates, one against the other. And the answers you get are very much based on the information, and the accuracy of it, that the laminate vendors give to you. In addition, the importance of these dimensions relative to their effect on the laminate you choose increases exponentially as you go up the speed curve of your end-product.

The Key Considerations for High Frequency, High Data Rate Designs

To get a better idea of how laminate choice impacts the overall design, manufacturability, reliability and life cycle of your highspeed design, it’s important to understand the three main characteristics that factor into these designs. They include:

• Impedance
• Loss
• Skew

Before we had these high frequency, high data rate designs, the thing that we worried about was just impedance and that the board didn’t fail. The factors that are now tied to laminate choices are loss and skew. In earlier times, the laminate suppliers didn’t provide very much information regarding the various characteristics and properties of their materials and typical values they did provide were basically useless. The information that is specified by IPC is about two pages in length and the two values provided are Dk and DF and they are defined as “typical”. This is the information that was being used by the fab shops without being able to take into account how the glass cloth in the supplied laminate affected these two properties. Further, there was no information relative to what the resin content was and at what frequency the typical data was measured.

As a result of the foregoing, there was only one way that we could determine how different laminates affected the foregoing operational concerns—building a test board. This resulted in the product design and development process being protracted and expensive. It was sort of like the PCB version of “whack a mole.” We just kept pounding until we finally found the best laminate for our particular design. And every time we tweaked a design in a particular area, trace widths for instance, we had to build another test board. This is likely where the practice of multiple respins of boards became an accepted cost and practice of doing business in the PCB world.

 The Tipping Point

To be fair, the foregoing factors really didn’t come into play until we started going up the speed curve. For me, it was when we were trying to design “the big iron” boxes that were used for Internet connectivity. At that point in time, the speed we were all trying to reach was 2.5 Gbps. We also didn’t have very good SERDES so 10 dB of loss was all that could be tolerated. This necessitated the building of test boards.

From an overall loss tangent standpoint, the factors that came into play (and still do today) are the length of the path and the noise tolerance of the ICs.

When the laminate suppliers did start providing us with loss information, the validity of their test data was very dependent on the test methodology used. There are two types of test methods – those that measure dielectric properties in plane (X/Y directions) and those that measure out-of-plane (Z direction). While there are some newer methods that have been developed, the primary methods that are in use are split post or split cylinder cavity, which measure in-plane and Bereskin (stripline), which measures out-of-plane. Because signals propagate in the Z-direction in TEM mode, the out-of-plane data, like what you get from Bereskin, is what is relevant for transmission lines. Split post cavity typically makes a material look much better than it really is. If you use that loss measurement data as your starting point, you will not have the correct data against which to measure your PCB. Bereskin test measurements are much more reliable.

And, to make matters worse, during this time, some laminate suppliers faked their data. The first data sheet I got with all of the different thicknesses of the laminate had a series of frequency columns. And no matter what square you looked at it said .002. We also didn’t have good information as to how much glass there was in the material or the glass to resin ratio. We did know that DF varies with glass content but we weren’t given that data.

Products operating at 2.5 Gbps were on the “bleeding edge” of the technology spectrum so there wasn’t yet a great incentive for the laminate providers to properly characterize their materials and provide that info to product developers.

Now, It’s All High Speed

As we started going up the speed curve, the problems that we encountered were rather like peeling an onion. You didn’t really know what the issues were going to be until you started your design and then built a test board. For instance, when we got to 5 Gbps, that’s when glass weave and the potential skew problems associated with it came into play.

As we move up the high frequency, high data rate design spectrum, we continue to find limitations in terms of how much room we have to play with when designing products. The reality is that the so-called wiggle room shrinks with each new speed increase.

Other Factors That Come Into Play

When you couple these elements into some of the common misconceptions that are associated with high-speed design it can be a real challenge in getting a product right the first time and every time thereafter.

For instance, there is this notion that very tight coupling of differential pairs is beneficial, but crowding traces closer together actually makes the loss go up. Then, there’s the idea that making the traces as wide as possible will minimize skin effect loss. The side effect of this is that to get to a 50-ohm impedance you have to have huge amounts of dielectric. This creates two negatives—the boards get very thick and the vias get much longer.

In order to somewhat debunk these “rules of thumb”, for another Internet product development process, we took the longest trace that was in the product. We had a tool that allowed us to separate the copper loss from the dielectric loss. We increased the traces from five mils to 10 mils wide and we plotted the dielectric by itself for three different loss tangents. It became glaringly evident that making the traces wider was a bad idea and it was a much better bargain to go with a low loss laminate.

Where Are We Today?

As our needs evolved and we hit hard on the material providers, the need for low loss laminates was mitigated when semiconductors were redesigned. We no longer needed to worry about loss and ordinary laminates sufficed for most designs. Then, the speed of the semiconductors was doubled and the loss issue came back into play because the increased device speed increased the amount of loss.

The reality is that the faster we go, the factors of loss and skew continue to be and actually increase the design challenge. For instance, if 56 Gbps links have any length at all, they have to be implemented in twinax because no matter how hard you work on the laminate weave, you will get into trouble with skew. There’s just no tolerance. This is because the bits are so narrow. At 56 Gbps, the whole bit period is 20 picoseconds long. The accepted theorem is that when your skew is ¼ of a big period, you are going to have errors. So, with a bit period of 20 picoseconds, five picoseconds of skew is going to cause problems. No matter what weave you choose, it will not be uniform enough to control the skew. Hence, the need for twinax.

Going Forward

It’s difficult for young engineers to get training at university on laminate properties and characteristics on high speed, high data rate designs. That means that they are left to attending industry conferences and getting training in their positions as they go along in their careers.

What does need to happen is for the industry to pull together in a new way. Product developers need to have better access to critical materials information and materials companies need to be more forthcoming with that information. In addition, fabricators need to help product developers determine that their designs are readily manufacturable. And, they likewise need more complete, detailed information from laminate suppliers. If we can all move forward in a more compatible, information-sharing based business model, the result will be a win-win-win for all concerned.