Key Manufacturing Issues Designers Need to Understand
As noted in numerous areas on the Avishtech website as well as tech journals, key conferences and a variety of other resources, today’s high frequency, high data rate designs necessitate the need for a much closer understanding of the factors between the design and manufacturing processes. Why this has become such a crucial topic is the extremely tight tolerances that are required to make designed PCBs, affordable, buildable, operable and reliable over the long haul of a product’s life cycle have very little “give” to them.
For this blog, I turned to the expertise and experience of a friend and colleague—Gerry Partida of Summit Interconnect. For the purposes of this article, we focused on five critical factors that impact the design-to-manufacturing link. They include:
- Minimum dielectric rules and when to make a new one.
- The removal of non-functional pads.
- Drill diameter versus the finished hole diameter.
- Microvias and reliability.
- Minimum copper required when the finished copper is specified.
This article will address these topics in sequence.
Gerry began his career in the PCB industry at Everett Charles Test Equipment. From there, he went to Optrotech/Orbotech. He was a member of the team that introduced several key advances to the industry including CAM automation, net list compare and AOI CAD reference.
Summit Interconnect (hereinafter referred to as Summit) was formed in 2016 following the acquisition of KCA Electronics and Marcel Electronics International (MEI). The goal was to create a well-capitalized custom circuit board company with advanced manufacturing capabilities and industry experts to provide a dependable domestic PCB source for the aerospace, defense and commercial markets. The company acquired Streamline Circuits in Santa Clara, California to provide manufacturing and support in the heart of the high-tech centric Silicon Valley. Summit is now one of the largest PCB companies in North America and approximately 65% of its business is in the aerospace and defense market sectors.
As Director of Technology at Summit Interconnect, Gerry’s focus is on cutting-edge high-density interconnect, high speed digital, Flex/Rigid Flex and RF microwave PCB fabrication for the company’s military and commercial customers.
He has been a certified IPC trainer as well as a member of the IPC-6012 and IPC-6018 review committees. Gerry explains, “I have been part of the IPC committees for the past 15+years. A lot of designers don’t realize that there are IPC specifications in the industry that we adhere to in our manufacturing operations and if we are sent a design that is not in line with those specifications then we can’t start the fabrication process. A key understanding that many designers may not have is that they sometimes need to ‘bend the rules a little’. This means that they also need to bend the final PCB requirements such that the finish requirement reflects the relaxing of these rules. We don’t expect them to have a complete understanding of all the relative specifications. They just have to have enough familiarity with them to make their designs manufacturable.”
So Many Specifications, So Little Time to Know Them All
The sheer number of IPC specifications applicable to the PCB design process can be, on first look, daunting. They include:
- IPC-2221 Design Guidelines for Printed Circuit Boards
- IPC-2222 Design Guidelines for Printed Circuit Boards for Rigid Boards
- IPC-2223 Design Guidelines for Printed Circuit Boards for Flex Rigid-Flex Performance Requirements
None of the foregoing specifications are “cast in stone.” As product requirements evolve so do the design specifications that are mandated for them. Gerry notes, “No one individual designer or even a group of designers will know all of these specifications inside and out, backwards and forwards so the question is figuring out which specifications are applicable to their particular design(s). The good news is that PCB manufacturers do know and understand how the requirements within these specs are levied.”
He continues, “There are all kinds of stages where product developers will engage with us. Some do it very early when they are doing the stackup and material selection and that’s very helpful for both us and them. The key things we need to know are the kind of drill spans they are using; whether or not they are using multiple sublams; where they are starting blind vias, buried vias and micro vias and if those vias are stacked or staggered.”
“The sooner they engage with us the sooner we can start guiding them through the design-to-manufacturing process and ask questions such as ‘why do you need all these structures?’ They assume having a lot of structures make it easier but it doesn’t as the more structures there are, the more multiple lam cycles there will be on the layer which makes the fab process more complicated and more expensive.”
For designers, it’s important to keep in mind that, at a minimum, the specs that are required are the applicable IPC-222X series design and the applicable IPC-601X series performance document. When a PCB does not comply with these or other equivalent documents then the acceptance requirements should be those agreed upon by the user (designer) and the supplier (manufacturer) which is specified as AABUS.
The Five Critical Factors
As noted above, this blog will address the five critical manufacturing factors in order.
Minimum Dielectric Layers
IPC 2222B states that when specifying the overall PCB thickness as well as the minimum dielectric thickness between layers, it’s important to take into account the effects of the accumulated dielectrics as well as the sublams (subcomposites) on the overall thickness of the board. If the minimum dielectric thickness is not specified and/or the number of specifying layers is not specified, the minimum thickness will be 90mm. If the nominal spacing on the drawings provided by the designer is less than 90mm, the dielectric spacing will be 25mm and the number of reinforcing layers may be selected by the supplier (manufacturer). If the core layers are less than 25mm, they are excluded from this requirement. Figure 1 shows how the minimum dielectric spacing is measured.
Figure 1. Measuring the minimum dielectric spacing.
With this rule as with the other four noted in this blog, Gerry says, “If the designers engage with us when they are going through the process of determining the overall thickness of their PCBs including the other accumulated dielectrics, then we can help them figure out what their designs need to have so that when those designs hit our facility, the process doesn’t come to a screeching halt.”
The Removal of Non-Functional Pads
The removal of non-functional pads (aka internal lands) and just when they can be removed is often an issue of confusion in the PCB design process. In a nutshell, in accordance with IPC 2222, these pads should never be removed for the purpose of making enough room to route a circuit between holes. To help maintain internal spacing, during the routing process, all of the non-functional pads/lands need to stay in place on all layers for each hole. After the circuits have been routed, the non-functional pads can be removed if desired.
The reason for the foregoing requirement is that non-functional pads/lands on plane layers can play an important role in maintaining the structural integrity of the PCB particularly when brittle resin systems are combined with thick copper and/or other foils. In these cases when the non-functional pads are removed, the small resin-rich areas may crack when exposed to drilling or thermal excursions. A non-functional pad provides a copper barrier between the hole and the clearance area that will insulate the resin rich area from the effects of hole formation. Prepregs with filled resins may be available to reduce the possibility of cracking when the non-functional pads are removed. The bottom line here is that the PCB manufacturer cannot arbitrarily remove the non-functional pads. It’s only allowed when the procurement document specifies it or when there is approval by the specific design authority.
Drill Diameter Versus Finished Hole Diameter
Probably one of the least understood factors in the design-to-manufacture to cycle lies in the difference between the drill diameter and the finished hole diameter. The difference between these two factors can be .004”-007” depending on the finish used on the PCB.
Taking this one step further, there is also confusion between the outside diameter and the inside diameter of a drill hole. Gerry explains, “If a customer wants a certain amount of annular ring, they need to understand that it is influenced by several factors including the copper plating and surface finish. I have to explain to them that with these two factors–copper plating and a surface finish–we fabricators drill 4-6 mils larger than the finished hole size to achieve the correct finish size. This means that the designer has to design the pad and annular ring for the drill size and not the finished hole size.”
Microvias and Reliability
One consideration that occurs today, particularly due to the types of boards being designed, is the reliability of microvias. One of the key challenges associated with them is that the failures associated with them might not crop up until later into the manufacturing cycle even after the PCB has met all the other specified lot conformance requirements. Typically, these failures occur during the assembly reflow processing operations and they are often undetectable at room temperature. And the further along that they occur during the assembly process the more expensive they become. And if they occur after the PCB has been put into operation, they are a much greater cost, and potentially, safety risk.
Based on the foregoing, a performance-based acceptance test in accordance with IPC-6012, Rev. E, 3.10.15, is recommended for all Class 3 PCBs that contain microvias.
Gerry notes, “The issue with microvias becomes a problem when you are stacking more than two of them. We have learned from reliability and reliability testing that you get consistently good results when you don’t stack more than two microvias.”
Minimum Copper If Finish Is Specified
The minimum amount of copper required when the PCB finish has been specified can be another source of confusion as to whether not the requirement refers to the copper weight or the thickness. Table 1 shows the various inner foil layer requirements after processing.
Table 1. IPC-6012, Table 3-14, Inner Layer Foil Thickness Requirements After Processing
This table is part of the IPC-6012 specification and it defines the minimum total (copper foil plus copper plating) for conductor thickness for the finished PCB. In addition, when a minimum thickness is specified for external conductors, the test coupon or PCB shall meet or exceed these minimum requirements. If the overall finish is specified in weight rather than thickness, the minimum conductor thickness after plating will be in accordance with the minimum foil after processing that is specified in this table for that particular copper weight.
Where Does Avishtech Fit Into The Scenario?
At Avishtech, the goal behind all of our toolset development efforts is enabling designers to have better insight into the design-to-manufacturing process. As an example, relative to the foregoing, our Gauss Stack toolset allows the designer to simulate Microvia Reliability for Reflow, Accelerated Testing, and Service Conditions, with just a few clicks. This is done through specifying the top and bottom layers of the via, along with the subjected thermal cycles and the diameter, pitch, and plating (if not filled) of the vias. Based on this data, Gauss Stack will, in seconds, provide the median cycles to failure or, if reflecting service conditions, median life to failure in terms of years of expected operating life, along with Stress and Strain curves. Gauss Stack accomplishes this by conducting a thermomechanical simulation specifically for the module or subassembly consisting of the layers starting at the top of the specified via and ending at the bottom of the specified via, followed by the relevant simulation of the via subjected to the specified thermal conditions.
The design-to-manufacturing link has become a crucial element within the overall PCB product development process. For designers, having a broadview understanding of what needs to be done on the design side for manufacturers to meet the specifications that are levied upon them enables the creation of a design that meets fabrication and functionality requirements and ensures that the resulting product will be manufacturable, operable and reliable the first time and every time thereafter. The key factor for success with this methodology is the designer communicating with the manufacturer early on in the design process and then continuing to leverage that communication throughout the entire design process as well as during the transition to the fabrication process.
Kella Knack currently serves as Director of Strategic Marketing for Avishtech, a leading provider of EDA software design tools–Gauss Stack and Gauss 2D. She assists in the company’s marketing communications, positioning, tradeshow, PR and outbound messaging efforts.
Prior to this, she served as Vice President of Marketing for Speeding Edge, an engineering consulting and training company focusing on the design of high speed PCB and system design. She oversaw the redesign of the company’s website; implemented the establishment of Speeding Edge as a publishing company; developed all of the company’s marketing materials and managed tradeshow activities. She also established key strategic relationships in Germany and Denmark and oversaw the expansion of the company’s presence in Europe, Canada and Asia. In addition, she served as editor and coordinated all layout and printing efforts for the publication of the company’s two technical books, “Right the First Time,” Volumes 1 and 2.
Before this, she was the Founder and President of KJ Communications, Inc., a marketing consulting and public relations company based in Silicon Valley. She served as a strategic adviser for a number of highly successful marketing campaigns for clients that ranged from start-ups to multimillion dollar companies in the EDA, networking, SOC IP, semiconductor, embedded system design and database management market sectors. Once the programs were defined, she assisted these clients by coordinating their press activities; preparing press releases and assisting with the development of other marketing materials. Before this, she was an editor of various industry technology publications including PCB Design, LAN Computing and ASIC and EDA Magazine.