Why PCB Design Should Adapt the Semiconductor Product Development Formula
///For as long as most of us can remember, creating a successful semiconductor has been based on the system-level design, verification and validation formula/approach to product development with the expectation that the product would work right the first time. The level of complexity applied to this design process was due to the vast amount of features and functionality inherent in a semiconductor and the high cost of “not getting it right.”
In contrast, PCB product development has often been a trial-and-error approach done with a certain level of simulation processes and toolsets done to better predict performance and reliability but always with an eye towards needing at least a few and often many prototypes and “respins” of a board. This was all done based on semiconductor and board design being two different processes with the expectation that the twain should never meet.
An Aside and Full Disclosure
Back in the late 1990s and into the early 2000s, I was the public relations and marketing consultant for Virtio. Virtio (which was eventually acquired by Synopsys) provided a web-based environment for the evaluation and customization of embedded systems. This technology enabled system designers to create a high-performance software model of a complete system without the need for physical hardware. The need for this prototyping kind of environment was driven, in part, by the IP that was being offered in the form of a large number of SoC product implementations. One of the bottlenecks in SoC design was the often time-consuming and error-prone process of evaluating multi-sourced hardware and software. Virtio’s platform addressed this need.
Semiconductor Design vs. PCB Design
A review of the current types of PCB products being designed; their increasingly tight design performance parameters; high levels of functionality within them and the realization that a failed product often means scrapping not only the PCBs but the components on them (often at the cost of tens of thousands of dollars for each component) emphasizes the need to review our decades old approach to PCB design.
When these factors are combined with the confluence of the perfect storm of market challenges of the past couple of years—a global pandemic, serious supply chain issues and the increasingly tentative political and territorial relationship between Taiwan and China, the mandate for critical thinking about the traditional PCB design approach becomes paramount. Based on the foregoing, and for a long time now, the need for detailed information about what’s going on in a component has been readily available but that insight has never been a part of the PCB design process.
This is based on the historical approach to PCB design. For boards, the process has usually involved an engineer doing component selection and then preparing the schematic and PCB layout. Then, just about the time that this individual is done with this effort a design review with a few of the other team members examines what’s been done to that point in time. It should be noted that this design review is often done under tight time constraints with the focus being on expediency and not quality. Unfortunately, at this juncture, it’s not possible to make changes to the design. As a result, the board is built and when it doesn’t meet specification requirements, the process has to start all over again. Increasingly, the expense of having to respin a board has far ranging costs, beyond the expected associated NRE efforts and costs. Ultimately, the cost of getting a product to market late can cause an individual product or line of products to fail.
The disparity between semiconductor and PCB design practices are inherent within the technology itself. For silicon product developers understanding the physical aspects of the technology and the functionalities they represent is a critical aspect to achieving a workable, reliable design. As an example, semiconductor designers create very detailed models for the resistance of a trace or the amount of capacitance. This type of model creation doesn’t take place within the PCB area.
As Lee Ritchey, Founder and President of Speeding Edge, notes, there are some challenges in PCB design that semiconductor product people don’t face. He states, “Most often, the physical size and configuration of the PCB is driven by the dimension of the end product. So, from the start, PCB developers are dealing with constraints that, on the surface, wouldn’t seem to affect the functionality of the board itself but ultimately they do.”
Ideally, at the beginning of the design process, PCB developers will create the architecture of the board. Ritchey notes, “There are lots of elements within the PCB design process that need to be addressed early on during the ‘architecture’ phase. One of the key ones is determining the power delivery system (PDS) design. A variety of factors have to be taken into account—the number of power supplies and their voltages and the amounts of current and load needed. The location of these supplies and their placement on each layer is mandatory to the design process. The reality is that PDS design accounts for the largest part of the design time and not getting these supplies and their voltage requirements correct has brought many PCB designs to a screeching halt.”
“Once the foregoing and other actions have been taken, it’s possible to do spreadsheet calculations of the resistance that is required and how much capacitance there is,” he continues. “These types of calculations and predictions, not a full-level detailed simulation will help in the creation of a good design that can then be handed off to a system-level tool such as Allegro (or whatever system-level tool is being used).”
As noted earlier, while system-level toolsets for both silicon and PCB design have been around for a long time, their parameters and capabilities differ significantly. System-level design, verification and validation address the plethora of actions that are going on the inside of any one chip such as the previously noted resistance of a trace and capacitance amount. There are a number of semiconductor design tools that address this but no similar tools for PCBs exist.
No surprise, the disparity between the level of detail and performance matrices of semiconductor and PCB toolsets are driven by a couple of different factors. First, the financial risk of failed silicon is magnitudes greater than that of PCBs. The cost of a bad chip is tens of millions of dollars. A mask set for some of the chip technology can run between $5-$10 million. This high cost of failure is part of the reason that the cost of semiconductors tools are at a much higher price point than PCB-level tools.
In contrast, the cost for building a PCB prototype can cost between $10,000-$30,000. So boards are typically built then the verification process is done. As a result, it is pretty much a given that trying to offer PCB design toolsets for millions of dollars would be, in its simplest form, a failed marketing approach. However, this is only part of the picture – the system level testing costs can easily run into several hundred thousand dollars per build and the hidden costs of delays and recalls due to reliability issues can run into tens of millions of dollars. These kinds of issues are far more common at the PCB level than at the semiconductor level, in large part because a system-level approach is not used.
But, with increasing frequency, we are approaching the point where the cost of a failed PCB is not just limited to the board itself. Ritchey explains, “It’s only when the costs of a failed board start impacting the silicon that people really start to sit up and take notice. You can’t recycle components off a failed board and use them on another. Given the increasingly tight parameters in today’s high frequency, high data rate designs, when you trash a PCB and the components which are mounted onto it, you are trashing an entire system design.”
“There really aren’t any good tools for all the actions that go on in a PCB,” Ritchey adds. “The electronic products being designed today have a lot of analog technology on the board with a lot of digital technology inside the chips.”
“When there are inductors in the power supply package that include both analog and digital functions and there is also a 20-amp supply, it’s a device that covers a spectrum of operations and can also cause a lot of challenges relative to PCB design,” Ritchey states.
Other Influencing Factors
The confluence of the perfect storm elements noted at the beginning of this article only add to the problem. Now, if critical components are trashed due to a failed board, it may take a year or longer to get more of them. This results in missed market windows and the potential loss of competitive market advantages.
The global pandemic, semiconductor supply shortages and the increasingly tense relations between China and Taiwan are contributing factors to the critical nature of the electronic design, manufacturing and assembly operations for both components and the boards onto which they are mounted. This confluence has exposed long-term weaknesses within the semiconductor sector. Bringing manufacturing stateside is a step in the right direction but it is not a magic bullet by any means nor is it possible at this point in time to predict how well this reverse migration of the industry back to the States will work.
Investing in and developing a new semiconductor manufacturing facility is not a simple matter. It’s a labor and capital expense intense process that requires volume manufacturing over a long period of time to make the effort pay off for all involved. And, the nature of the evolution of the electronics industry is such that once a technology matures, the prices for a commercially-available part can fall off dramatically. When this is combined with the inherent challenges in building and bringing a new manufacturing facility up to speed, the availability of a particular component can quickly become a big issue not just for the manufacturing company but the customers who are relying upon it being around for the long haul.
There is no written rule that a component manufacturer has to inform its customers that it is going to be stopping production on a particular product. If there is no “last time buy”, footprint compatible components or other suppliers of a technology available, a company bringing a multi-million dollar piece of equipment to market can find that it can’t ship its products all because of the lack of availability of a $5.00 part.
This then brings another factor into the equation. There are a number of parts that go into a system that sell for $1-$2. When the companies supplying these parts can’t make money off of them due to one or several factors, companies designing and building really expensive pieces of equipment won’t design in these critical, low-cost parts until they can purchase two years’ worth of them that they can keep on the shelf.
How Avishtech Addresses the Foregoing
While no one company can address everyone’s needs, Avishtech continues to leverage and build upon the technology already in our toolsets. This includes taking a much more comprehensive approach to tool development incorporating a number of parameters and bringing them forward to help with the design of current as well as future PCB products. Thus far, we have already incorporated a number of parameters and brought them forward as critical features and functionality that relate to downstream processes. Now, we are looking at “lessons learned” from other aspects of the electronic product development process, such as semiconductor design and development, and are actively adopting and adapting them as they can be applied to the PCB design process.
Kella Knack currently serves as Director of Strategic Marketing for Avishtech, a leading provider of EDA software design tools–Gauss Stack and Gauss 2D. She assists in the company’s marketing communications, positioning, tradeshow, PR and outbound messaging efforts.
Prior to this, she served as Vice President of Marketing for Speeding Edge, an engineering consulting and training company focusing on the design of high speed PCB and system design. She oversaw the redesign of the company’s website; implemented the establishment of Speeding Edge as a publishing company; developed all of the company’s marketing materials and managed tradeshow activities. She also established key strategic relationships in Germany and Denmark and oversaw the expansion of the company’s presence in Europe, Canada and Asia. In addition, she served as editor and coordinated all layout and printing efforts for the publication of the company’s two technical books, “Right the First Time,” Volumes 1 and 2.
Before this, she was the Founder and President of KJ Communications, Inc., a marketing consulting and public relations company based in Silicon Valley. She served as a strategic adviser for a number of highly successful marketing campaigns for clients that ranged from start-ups to multimillion dollar companies in the EDA, networking, SOC IP, semiconductor, embedded system design and database management market sectors. Once the programs were defined, she assisted these clients by coordinating their press activities; preparing press releases and assisting with the development of other marketing materials. Before this, she was an editor of various industry technology publications including PCB Design, LAN Computing and ASIC and EDA Magazine.